1. Field of the Invention
The present invention relates to a direct memory access controller with a filter for filtering data during transport of the data from a source memory to a destination memory.
2. Description of the Related Art
Direct Memory Access (DMA) controllers are specialized processors used for transferring data between a source memory and a destination memory, thereby allowing a Central Processing Unit (CPU) to simultaneously perform other tasks. Referring to FIG. 1, a standard DMA controller 10 interfaces directly with a source memory 1 and is connected via a bus 8 to a destination memory subsystem 3. The DMA controller 10 includes a source memory control 2, a destination bus control 4 and a first-in-first-out memory device (FIFO) 5. The external CPU initiates data transfer in the DMA controller by setting up DMA registers with a memory address at which the data of interest is located in the source memory 1, a memory address of the destination memory at which to start the transfer to the destination memory 3, and the number of bytes to be transferred.
The source memory control 2 starts to read data from the source memory 1 and stores the read data in the FIFO 5. At the same time, the destination bus control 4 arbitrates for the bus 8 and then starts to transfer data from the FIFO 5 across the bus 8 to the destination memory subsystem 3. The DMA controller 10 is external to the CPU and the destination bus control 4 acts as a master on the bus 8 which is connected to the destination memory 3. When the specified amount of data has been transferred, an interrupt is raised or status word updated to indicate completion.
The above-described DMA controller 10 may be used, for example, in a network analyzer. In such an implementation, the source memory 1 is a capture buffer of the network analyzer and the destination memory subsystem is a part of a host PC which includes the CPU that operatively initiates the data transfer to the destination memory, i.e., the CPU memory of the host PC. The network analyzer is a test system that analyzes links and must capture data from the link being analyzed into a capture buffer. After capture, some or all of the data may need to be transferred to the system memory of the host PC (i.e., the destination memory). It may be desirable for only certain parts of the data are to be transferred to the destination memory. The location of the required data in the capture buffer memory may not be known. But, for efficiency of operation it is preferred that only those frames or packets of data that are needed be uploaded from the capture buffer memory to the destination memory.
One problem with the above-described prior art implementation is that all of the captured data is typically transferred from the source memory to the destination memory without regard to the data content. If the location in the buffer memory of the required data is not known, all of the data must first be transferred to the destination memory and the transferred data must then be searched in the destination memory until the required data is identified. Accordingly, a large portion of the data transferred may be discarded.
U.S. Pat. No. 6,266,789 to Bucher et al. (Bucher) discloses a buffer memory system for a protocol analyzer that includes a capture buffer memory for receiving data from a link via an interface. A host port connects the capture buffer to a host processor having a memory and a processor. The protocol analyzer disclosed in Bucher also includes a search engine that searches the buffer memory for data matching a desired memory pattern. When the memory pattern is found, reading of the memory is halted and a match signal is generated. The user can then determine the location of the match in the buffer memory and access the matching data.
The Bucher reference requires a three step process controlled by software on the host computer to transfer the required data: (1) initiate the search, (2) interrogate the analyzer to retrieve the current data read address, and (3) setup and initiate the DMA controller to transfer the required data based on that address. Furthermore, Bucher searches for a single match and, therefore, the three part process must be repeatedly rerun, making it unnecessarily time consuming and cumbersome when multiple pieces or segments of data must be transferred.
Bucher also teaches that a filter, in the form of logic circuitry, may be applied to selectively write data from the interface to the data buffer memory. One problem with the filtering in Bucher is that it operates upstream of the data buffer to thereby limit the data being captured and stored. It is not, therefore, possible to vary the filter conditions to analyze or view data that has already been eliminated through filtering.